Jitter Reduction Using PLL and ASRC Devices

A/D and D/A converters require very low-jitter clocks to achieve 20-bit to 24-bit precision. In contrast, digital audio interfaces such as S/PDIF, AES, ADAT, USB, and Firewire can tolerate large amounts of jitter without any loss of data. These interfaces deliver the data intact, but fail to deliver the low-jitter clock needed for conversion. It is important to understand that clocks that are embedded on digital audio interfaces are not suitable for directly driving the sampling circuit inside a high-performance A/D or D/A converter. Clock-filtering or clock-isolation is required to achieve high-performance.

Interface clocks can be filtered with a “phase-locked-loop” (PLL) to produce a low-jitter sampling clock. In such a system, jitter attenuation is determined by the frequency response of the PLL loop filter. This filter is a low-pass filter that rejects high-frequency jitter. Jitter at frequencies above the PLL cutoff frequency will be attenuated while jitter at frequencies below the PLL cutoff frequency will be untouched. From a jitter standpoint, the ideal PLL loop filter has a very-low cutoff frequency, and a steep slope above the cutoff frequency. Unfortunately, higher cut-off frequencies are often required to achieve reasonable lock times. Furthermore, PLL frequency ranges are often very limited in a high-performance system. A PLL-based system must establish a good compromise between performance and usability.

Instead of filtering a clock with a PLL, we can create an entirely separate fixed-frequency low-jitter clock that is used exclusively for driving the sampling circuit. Audio data must then be moved between the high-jitter digital audio interface and the low-jitter sampling system. An “asynchronous sample rate converter” (ASRC) can be used to move the data between these two clock domains. The two clock frequencies can be completely different, yet it is still possible to accurately resample the audio to the new clock domain.

The accuracy of an ASRC re-sampling process is largely determined by our signal processing budget. Many ASRC devices have enough DSP horsepower to hold errors to levels that are 130 to 150 dB below the audio. The distortion caused by these devices is well below the threshold of hearing – even at extremely high playback levels.

A high-resolution ASRC may fail to achieve transparent performance if it has poor jitter attenuation. However, if properly designed, the transparency of an ASRC can be maintained in the presence of jitter. Such an ASRC device can be used to attenuate jitter when passing audio between two clock domains. Some ASRC devices (such as the AD1896) have excellent jitter attenuation while others (such as the SRC4192) have very little jitter attenuation. The AD1896 has 100 dB jitter attenuation at 1 kHz while the pin-compatible SRC4192 has 0 dB jitter attenuation at 1 kHz. This vast difference in jitter performance is due to the behavior of the “rate estimators” inside the ASRC devices.

The rate estimator in an ASRC measures the ratio between input and output sample rates. This ratio is used to control the re-sampling process inside the ASRC. The jitter attenuation of an ASRC is determined by the frequency response of the rate estimator. Jitter at frequencies above the rate-estimator cutoff frequency will be attenuated while jitter at frequencies below the cutoff frequency will be untouched. The rate estimator in the AD1896 has a 1 Hz cutoff frequency and 100 dB jitter-attenuation at 1 kHz. The AD1896 is so effective as a jitter attenuator that jitter-induced distortion is held to levels below -135 dB FS with any of the audio interfaces mentioned at the beginning of this paper. Jitter-induced noise and distortion are held well below audibility under all operating conditions. Similar jitter-attenuation performance is difficult (but not impossible) to achieve with a conventional PLL system.

Let’s review the key points:
• A/D and D/A converter sampling circuits require very low-jitter clocks
• PLL circuits can be used to clean up a high-jitter clock
• The frequency response of the PLL loop filter determines jitter attenuation
• PLL loop filter requirements may conflict with other system requirements
• A dedicated low-jitter clock domain can be created for the A/D or D/A sampling circuits
• An ASRC can be used to move audio between the high-jitter and low-jitter clock domains
• An ASRC process can be very transparent if we use enough DSP “horsepower”
• ASRC performance can be degraded by jitter if it is not designed to reject jitter
• ASRC jitter-attenuation is determined by the frequency response of the rate estimator
• Some ASRC devices have excellent jitter attenuation, others do not
• The jitter attenuation of the AD1896 exceeds the performance of most PLL systems

What is the difference between an ASRC and a SRC?

A “synchronous sample rate converter” (SRC) is essentially an ASRC without a rate estimator. The DSP filter coefficients in an SRC are never altered by jitter. In contrast, the DSP filter coefficients in an ASRC are dynamically controlled by the rate estimator. Jitter can cause instantaneous changes in the sample-rate ratio calculated by the rate estimator. If these jitter-induced ratio changes are allowed to instantaneously change the DSP filter coefficients in the ASRC, jitter-induced distortion is encoded into the output samples. For this reason, some ASRC devices have a low-pass filter on the rate estimator subsystem. This low-pass filter determines the jitter attenuation of the ASRC. As the corner frequency of the rate estimator approaches DC, the ASRC approaches the function of a synchronous SRC, rejecting all jitter.

What happens to the audio when jitter is not removed by the ASRC?

ASRC devices with poor jitter-attenuation create a nasty problem: Any jitter that is not removed by the ASRC will be permanently encoded into the data at the output of the ASRC. This encoded jitter-induced distortion becomes a permanent part of the audio signal that cannot be removed by a subsequent process. Some critics have claimed that ASRC devices “change jitter into amplitude errors” or “change jitter into distortion”. This is only true for ASRC devices that lack adequate filtering in the rate-estimator inside the ASRC. Jitter at frequencies above the corner frequency of the rate-estimator filter will be attenuated. Jitter at frequencies below the corner frequency of the rate-estimator filter will be converted into distortion. The frequency response of the rate-estimator filter determines the jitter attenuation of an ASRC device. For this reason, it is very important to select an ASRC with a well designed filter on the rate-estimator subsystem.

Let’s look at an example of an ASRC jitter-attenuation system:

The Benchmark DAC1 uses an AD1896 ASRC to attenuate jitter. This ASRC device is very effective at attenuating jitter to levels that are well below audibility. The effectiveness of this system can be verified using an FFT spectrum analyzer. Some aftermarket modifiers have substituted the pin-compatible SRC4192 into the DAC1 (in hopes of improving the performance). In doing so, they have completely destroyed the jitter-attenuation performance of the DAC1. It is relatively easy to verify the performance degradation caused by this component substitution. The difference in jitter-attenuation can easily be observed using the FFT spectrum analyzer on an Audio Precision test system. Jitter-induced sidebands are produced whenever the system with the SRC4192 is exposed to jitter. In contrast, the spectrum of the stock DAC1 (with AD1896) remains clean when exposed to jitter. An ASRC can turn jitter into distortion when the wrong ASRC device is selected!

In the DAC1, the input side of the ASRC is exposed to the noisy S/PDIF or USB clock. The output side of the ASRC is driven by a very clean, low-jitter clock that is used to drive the sampling circuit in the D/A circuit. At the input of the ASRC, we have clean data riding on a noisy clock. When the AD1896 is in the circuit, the AD1896 delivers clean data, on a clean clock. In contrast, if an SRC4192 is in the circuit, the SRC4192 delivers distorted data on a clean clock. In both cases, the D/A clock is clean and jitter-free. The difference is that the AD1896 produces a clean output spectrum while the SRC4192 produces an output spectrum that has jitter-induced phase modulation (jitter-induced distortion). The jitter-induced distortion produced by the SRC4192 is identical in amplitude and frequency to the distortion that would have been produced in the D/A circuit if it was driven directly from the high-jitter interface clock. The SRC4192 simply converts jitter into distortion – giving fuel to the armchair critics of ASRC-based jitter attenuation. In contrast, the AD1896 removes the jitter without adding jitter-induced distortion. The AD1896 is so effective that jitter-induced distortion never exceeds -135 dB FS when the input of the DAC1 is subjected to extreme levels of jitter. The DAC1 manual has plots that show no change in performance when inserting 1000 feet of digital cable, and no change in performance when adding a 12.5 UI jitter signal to the input. USB audio interface jitter is absolutely not an issue with this system.

Non-standard sample rates:

An added benefit of the ASRC system in the DAC1 is that the converter will instantly lock to any sample rate between 28 kHz and 195 kHz. Non-standard sample rates resulting from video pull-up or pull-down are not a problem. The DAC1 is also one of very few converters that are compatible with transports that have pitch controls. PLL-based systems usually cannot lock to a pitch-controlled transport. Jitter attenuation is very important when using pitch control because most transports tend to have high jitter while pitch control is active.