Phase lock
From Benchmark
This article discusses the logistics and technology associated with phase locking multiple digital converters.
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John Siau's forum post regarding Phase lock
This quote is from John Siau's post on the PSW recording forum
The matched-phase mode of the AD1896 SRC is required when downconverting, but is not required when upconverting. When upconverting, the AD1896 has a fixed delay that is a function of the input sample rate only. The phase relationship between the input and outputs clock will not change the delay through the SRC. The SRC filter coefficients are always selected to maintain a constant delay from the average phase of the input clock signal. The averaging function prevents jitter artifacts, and is one of 3 significant advantages provided by an upsampling SRC topology.
In the Benchmark DAC1 the AD1896 is upsampling, and the delay is a function of the input sample rate, and the fixed-frequency conversion clock. The input sample rate determines the delay through the SRC, and the conversion sample rate determines the delay through the D/A converter IC (AD1853). In a multi-channel system, the digital signals feeding multiple DAC1 converters are all derived from the same clock, and are in phase. However, the internal conversion clocks (inside the DAC1 boxes) are all running independently and yet phase accuracy is maintained (see the plots in the manual or at the link provided earlier in the thread). The phase accuracy between two DAC1 boxes is only a function of the frequency matching of the two independent fixed-frequency conversion oscillators. These are crystal oscillators and are actually much more closely matched than they need to be. They are matched to +/- about 50 PPM (+/- 0.005%), and if we do the math, this corresponds to +/- 0.004 degrees at 20 kHz. The analog circuits (and the measurement equipment) have orders of magnitude more phase error than the SRC & D/A conversion systems in the DAC1.
In summary, it is possible to have phase accuracy between boxes, and the DAC1 box-to-box phase measurements prove this.
Multiple DAC1 boxes are phase accurate up to an input frequency of 110 kHz. We do not claim phase accuracy between boxes at 176.4 or 192 kHz.
[quote] I was giving some perspective on the clock accuracy figures for those here not familiar with the numbers and that for IP SR's below 110k it *may* be an advantage to have a tighter spec than 50ppm when multiple DA are summed. Just to make a further point for others, this +-50ppm has NO reflection on jitter performance of clock. [end quote]
The delay on the 110 kHz side of the SRC is 1.01 ms +/- 50 ppm. The +/- 50 ppm variation is due to the +/- 50 ppm variation in the oscillator used for the 110 kHz D/A conversion clock.
50 ppm is 0.00005
0.00005*1.01 ms = 50.5 ns
50.5 ns is equivalent to moving the position of a microphone by 0.00005 feet, and is equivalent to the electrical delay through a 25 foot cable.
At 20 kHz, +/- 50.5 ns is:
50.5E-9*20000*360=0.36 degrees (at 20 kHz)
This +/- 0.36 degree variation is insignificant, even when the channels are summed.
The amplitude error after summing is: 20*Log((cos(0.36*2)+cos(0))/2)=-0.00035 dB at 20 kHz
What about comb filtering? The first null in the comb filter will occur no lower than: 1/(2*50.5 ns/2)= 19.8 MHz
The bandwidth of 96 kHz digital audio is limited to 48 kHz, so a null at 19.8 MHz is of no consequence.
Substituting more accurate crystal oscillators should give disappointing results and may damage the multi-layer circuit board. The heavy ground planes on the DAC1 make it very difficult to replace the oscillator without damaging the board.
